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circuit note cn-0385 circuits from the lab? reference designs are engineered and tested for quick and easy system integration to help solve todays analog, mixed-signal, and rf design challenges. for more information and/or support, visit www.analog.com/cn0385 . devices connected/referenced ad4003 18-bit, 2 msps, pulsar?, 7.0 mw adc in msop/qfn AD8251 10 mhz, 20 v/s, g = 1, 2, 4, 8, i cmos programmable gain instrumentation amplifier adum141e robust, quad channel isolator with output enable and 1 reverse channel adg5207 high voltage, latch-up proof, 8-channel differential multiplexer ad8475 precision, selectable gain, fully differential amplifier ada4807-2 3.1 nv/hz, 1 ma, 180 mhz, rail-to-rail input/output dual op amp isolated, multichannel data acquisition system with pgia for single-ended and differential industrial level signals rev. 0 circuits from the lab? reference designs from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance ha ve been tested and verified in a lab environment at room temperature. however, you are solely resp onsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits fr om the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2016 analog devices, inc. all rights reserved. evaluation and design support circuit evaluation boards cn-0385 circuit evaluation board (eval-cn0385-fmcz) system demonstration platform (eval-sdp-ch1z) design and integration files schematics, layout files, bill of materials circuit function and benefits the circuit shown in figure 1 is a cost effective, isolated, multi- channel data acquisition system that is compatible with standard industrial signal levels. the components are specifically selected to optimize settling time between samples, providing 18-bit performance at channel switching rates up to approximately 750 khz. the circuit can process eight gain-independent channels and is compatible with both single-ended and differential input signals. the analog front end includes a multiplexer, programmable gain instrumentation amplifier (pgia); precision analog-to- digital converter (adc) driver for performing the single-ended to differential conversion; and an 18-bit, 2.0 msps precision pulsar? adc for sampling the signal on the active channel. gain configurations of 0.4, 0.8, 1.6, and 3.2 are available. the maximum sample rate of the system is 2 msps in turbo mode, and 1.5 msps in normal mode. the channel switching logic is synchronous to the adc conversions, and the maximum channel switching rate is 1.5 mhz. a single channel can be sampled at up to 2 msps with 18-bit resolution in turbo mode. channel switching rates up to 750 khz also provide 18-bit performance.
cn-0385 circuit note rev. 0 | page 2 of 13 figure 1. isolated multichannel data acquisition simplified circuit (all connections and decoupling not shown) circuit description the circuit shown in figure 1 is an isolated multichannel data acquisition signal chain consisting of a multiplexer, programmable gain stage, adc driver, and a fully differential, precision, successive approximation register (sar) adc. the channel switching and gain switching is synchronized to the conversion period of the adc. the system can monitor up to eight channels using a single adc, reducing component count and cost compared to systems with one adc per channel. each channel can be configured with a different gain, allowing for flexibility of input ranges. it is manipulated by the complex programmable logic device (cpld) which can be configured in the labview graphical user interface (gui). the effective sample rate for each channel is equal to the sample rate of the adc divided by the total number of channels being sampled. the maximum sample rate of the system is limited by the settling time of the components (such as the programmable gain amplifier (pga) bandwidth and rc filter bandwidth) in the analog front end and the isolated digital interface clock rate which runs at 75 mhz. multiplexed signals are discontinuous in nature, resulting in potentially large voltage steps between sampling intervals. the components in the signal chain must be given adequate time to settle to these steps before the adc performs a conversion. to maximize the time given for the signal to settle, the multiplexer channels are switched immediately after the adc begins a new conversion. the board power supply can take a dc input from 5 v to 12 v at the dc jack or 12 v from the sdp-h1 controller board. the adp2441 dc-to-dc converter generates 3.3 v for the digital interface and the adum3470 primary supply input. the adp5070 , adp7118 , and adp7182 are used to generate positive and negative 15 v supplies. the adp7118 is used to generate 5 v, 3.3 v, and 1.8 v for the analog and digital power supplies. the adum141e is selected for isolated high speed spi communication. it has 150 mbps maximum data rate, low propagation delay, and low dynamic power consumption. component selection the adg5207 is a high voltage, latch-up proof, 8-channel differential multiplexer. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. a switching network at the inputs of the adg5207 adds compatibility with both single-ended and differential input signals. the active channel is selected via the address pins of the device, which are controlled by the cpld, and which can be configured in the gui. the AD8251 is a programmable gain instrumentation amplifier that provides selectable gain settin gs of 1, 2, 4, and 8. the higher gain settings boost smaller input signals to the full-scale input range of the ad4003 . each gain setting has its own suitable input range, which is shown in table 1. table 1. input range for each of the four gain configurations gain full-scale input range 0.4 10.24 v 0.8 5.12 v 1.6 2.56 v 3.2 1.28 v 1-of-8 decoder c0+ c7+ adg5207 vdd +15v ?15v da ad8475 adum3470 adp2441 fmc adum141e ? + ? + ?in_0.4 ?in_0.8 vcom +in_0.8 +in_0.4 1.25k ? 1.25k ? 1.25k ? 1.25k ? 1k? 1k? 4.99k ? 4.99k ? +v s ?v s out+ 200 ? 120pf 120pf 200 ? out? 1/2 ada4807-2 1/2 ada4807-2 100 ? 100pf 100 ? 100pf +in ?in ad4003 ref vdd vio gnd sck sdo sdi cnv sck sdo sdi cs cnv adp5070 adp7118 5.5v +16v +15v adp7118 5v 5.5v 5.5v adp7118 1.8v adp7118 3.3v adp7182 ?15v ?16v AD8251 + ? + ? ? + ?in +in +v s ?v s ?15v +15v logic + ? dgnd wr a1 a0 a1 a2 en gnd vss a0 out ref ?5v +5v +5v c7? c0? db 100 ? 100pf 100 ? 100pf 2.2f 5v 2.2f 5v adr4540 tp nc7 vout nc5 nc1 vin nc3 gnd cpld sdi sck sdo cs 10f 0.1f 1.8v 3.3v 5.5v 3.3v 12v 15142-001
circuit note cn- 0385 rev. 0 | page 3 of 13 the ad8475 funnel amplifier provides high precision attenuation (0.4), accurate common - mode level shifting, and single - ended to differential conversion. its low output noise spectral density (10 nv/hz) and fast settling time (50 ns to 0.001% for a 2 v output step) make it well suited to drive the ad4003 . the ad4003 is a fully - differential, 2 msps, 18 - bit precision sar adc that features a typical signal - to - noise ratio ( snr ) of 98 db when using a 4.096 v reference. the ad4003 is also low power, and only consumes approximately 17 mw at full throughput. its power consumption scales with throughput, and can operate at lower sa mple rates to cut its power use (for example, 0.17 mw at 100 ksps). system dc accuracy errors figure 2 shows the ideal transfer function of the data a cquisition system. figure 2 . adc ideal transfer function each of the components in the data acquisition signal chain adds its own offset error and gain error that cause the real transfer function of the system to deviate from the ideal transfer function shown in figure 2 . the cumulative effects of these errors can be measured at a system level by comparing known dc inputs near zero and full scale at the input to the adg5207 (rc filter if it is present) and the resulting output codes from the ad4003 to obtain a system calibration factor. offset error measurement for ideal bipolar, differenti al adcs, a 0 v differential input results in an output code of 0. real adcs typically exhibit some offset error ( b ), which is defined as the deviation between the ideal output code and the measured output code for a 0 v input. the offset error for the data acquisition system can be found by grounding its input and observing the resulting output code. this error varies between each of the gain settings of the AD8251 and between each of the channels of the adg5207 . offset error is therefore measured for each of the channels in all four gain configurations. because the system monitors multiple channels, it is also important to quantify the amount by which the offset error deviates between channels. offset error match ( b, max ) is a measure of the max - imum deviation between the offset error of each of the channels and the average offset error of all of the channels. offset error match is calculated using the following equation: ) 7 ..., , 1 , 0 | ) 8 (max( 7 0 , , , = ? = ? = i j j b i b max b where b,i and b,j are the offset errors for the i and j channels, respectively. this offset error match can be found for each of the gain configurations. not e that offset error can be expressed either in codes or volts. gain error measurement error in the gain of the system also contributes to overall system inaccuracy. the ideal transfer function of the ad4003 is shown in figure 2 , where the ?2 17 and 2 17 ? 1 output codes correspond to a negative full - scale input voltage (?fs) and a positive full - scale input voltage (+fs), respectively; however, the combination of offse t error ( b ) and gain error ( m ) results in a deviation from this relationship. gain error can be expressed as a percentage error between the actual system gain and the ideal system gain. the more common expression is in percent full - scale error (%fs), whi ch is a measure of the error between the ideal and actual input voltages that produces the 2 17 ? 1 code. the ideal full - scale input voltage ( v fs, ideal ) is a function of the resolution of the adc (18 - bits for the ad4003 ) and the accuracy of the reference voltage ( v ref ). errors in the voltage reference translate to gain errors in the adc. to decouple reference errors from adc gain error, v ref is measured using a precision multimeter. the ideal full - scale input voltage can then be calculated using meas ref meas ref ideal fs v v v , 17 , 18 , 2 2 2 = = y real = m lr v in the real full - scale input voltage ( v fs, real ) can then be calculated using lr lr real real fs m m y v 17 , 2 = = ? = ideal fs real fs ideal fs m v v v the gain error of the system varies with the gain of the AD8251 , but is channel independent. therefore, gain error is measured for each of the four gain configurations, but only using one of the adg5207 channels in this system. 100...000 100...001 100...010 0 1 1...101 0 1 1... 1 10 0 1 1... 11 1 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 15142-002
cn- 0385 circuit note rev. 0 | page 4 of 13 system noise analysis one of the key design goals in precision data acquisition systems is achieving a high snr, which can be achieved by increasing the full - scale signal amplitude and/or by decreasing the noise power generated by the components in the system. the total noise power present in the system can be found by taking the root sum square (rss) of the noise power contributed by its individual components, referred to the input of the ad4003 : 2 2 , 2 , 2 5 , , ad4003 n, ad8475 n AD8251 n 207 adg n total n v v v v v + + + = ? ? ? ? ? ? ? ? = total n ref expected v v snr , 2 log 20 the expected noise contributions for each component in the system and the resulting expected snr performance of the whole system is shown in table 2 . the total system noise calculation ignores thermal noise contributed by the passive components in the system. noise due to the ad4003 adc the noise of the ad4003 adc is a function of both its inherent quantization error and noise caused by internal components (such as passive components producing thermal noise). the rms input voltage noise of the ad4003 can be calculated from its specified snr using ? ? ? ? ? ? = 20 , 4003 10 2 ad snr ref ad4003 n v v the snr for the ad4003 snr ad4003 is specified as approximately 8 db for a 4.0 v reference. the single - pole rc filter at the input of the ad4003 limits the wideband noise from the upstream components. a smaller filter bandwidth improves snr by further limiting noise power however, its time constant must also be sufficiently short to settle voltage kickbacks due to charge injections that occur as the ad4003 inputs reconnect to the front - end circuitry during the acquisition phase. the appropriate bandwidth for the system is at least 5 mh for more information , see the analog dialogue article, front - end amplifier and rc filter design for a precision sar analog - to - digital converter ). noise due to the ad8475 funnel amplifier the rms noise contributed by the ad8475 ( v n, ad8475 ) is a function of its referred to output noise spectral densit y (nsd) ( e ad8475 ) and the rc filter bandwidth at the input to the ad4003 ( bw rc ): rc ad8475 ad8475 n, bw e v = 2 where e ad8475 = 10 nv/hz. noise due to the AD8251 instrumentation amplifier the AD8251 functions as a gain stage that improves snr for small amplitude signals by boosting their amplitude to more closely fill the v ref range at the input to the ad4003 . ideally, if the system gain increases by a factor of g , the snr (in db) of the input signal improves by snr = log 10 ( g ) t his level of improvement is not achievable in reality, however, because wideband noise is also amplified by the noise gain of the circuit. fortunately, this degradation is not as large as the improvement due to signal gain. the rms noise contributed by the AD8251 is a function of its referred to input nsd ( e AD8251 ), its gain setting ( g AD8251 ), the attenuation factor of the ad8475 ( g ad8475 ) , and the noise filter bandwidth at the input of the ad4003 : rc ad8475 AD8251 ad n bw g g e v = 2 8251 ad 8251 , the value of e AD8251 is also dependent on the AD8251 gain ; the value of e AD8251 can be found in the AD8251 data sheet . noise due to the adg5207 multiplexer the nsd and resulting rms noise contributed by the adg5207 can be found by using the johnson/nyquist noise equation, because the device acts like a series resistance between the source and the re st of the analog front end: on b 207 adg n, r t k e = 4 5 and rc ad8475 AD8251 207 adg n, 207 adg n, bw g g e v = 2 5 5 the resistance of each channel ( r on ) can be found in the adg5207 data sheet. a summary of the calculated noise perfor mance of the system is shown in table 2 . the largest contributors to the total noise are the AD8251 in - amp and the ad4003 adc.
circuit note cn- 0385 rev. 0 | page 5 of 13 table 2 . noise performance for the multichannel data acquisition system adg5207 AD8251 ad8475 ad4003 total g ain e n , adg5207 (nv/hz) v n , adg5207 (v rms) e n , AD8251 (nv/hz) v n , AD8251 (v rms) e n , ad8475 (nv/hz) v n , ad8475 (v rms) v n , ad4003 (v rms) v n , total (v rms) snr (db) 0.4 2.04 2.29 40 44.7 10 28 35.4 63.6 93.2 0.8 2.04 4.57 27 60.4 10 28 35.4 75.5 91.7 1.6 2.04 9.15 22 98.4 10 28 35.4 108.6 88.5 3.2 2.04 18.3 18 161 10 28 35.4 168.2 84.7 settling time analysis when the circuit shown in figure 1 is sampling multiple channels, each of the different inputs are merged into a time - division multiplexed signal by the adg5207 . multiplexed signals are discontinuous in nature, and typically have large voltage steps occurring in short time intervals. for the system in figure 1 , the voltage differential between two consecutive channels may be as large as 20 v at the inputs of the adg5207 , and the time allotted for settling is only as long as the sampling period. figure 3 shows the settling time model of the circuit in figure 1 . each of the components in the system has its own settling characteristics (see the following sections). figure 3 . settling time model of cn - 0385 circuit settling time is defined as the time required for the analog front - end circuitry to settle an input step to a certain precision. this precision is usually specified in percent erro r (for example, 0.1% or 0.01%); however, in conversion systems , it is also helpful to relate it to resolution. for example, settling to a 16 - bit resolution is roughly equivalent to settling to 0.001%. table 3 shows the relationship between settling to percent error and to resolution for a single - pole system. table 3 . percent error and effective r esolution resolution, no. of bits lsb (%fs) no. of time constants = ?ln (% error/100) 6 1.563 4.16 8 0.391 5.55 10 0.0977 6.93 12 0.0244 8.32 14 0.0061 9.70 16 0.00153 11.09 18 0.00038 12.48 20 0.000095 13.86 22 0.000024 15.25 estimating the settling time of an analog front end with multiple components is not trivial for a variety of reasons. first, many devices do not specify settling characteristics to very high precision. settling time for an active device is also not linearl y related to settling precision, and it may take up to 30 times as long to settle to 0.01% as to 0.1%. the settling time can be due to long - term thermal effects inside the amplifier. settling time is also dependent on the load that the device is driving, a nd settling time is generally not characterized for multiple load conditions. measuring high precision settling is also difficult without a specialized characterization platform, because of the effects of oscilloscope overdrive and sensitivity, and the dif ficulty of generating an input pulse with sufficient rise time and settling time. settling time can be estimated provided certain bounds and assumptions are used in analyzing the circuit. the total settling time can be calculated by taking the rss of the s ettling times of the individual components: 2 s_ad4003 2 s_ad8475 2 s_AD8251 2 s_adg5207 _ t t t t t total s + + + = _ 1 < settling time of the adg5207 the equivalent circuit for a cmos switch can be approximated as an ideal switch in series with a resistor (r on ) and in parallel with two capacitors (c s , c d ). the multiplexer stage and assoc iated filters can therefore be modeled as shown in figure 4 . figure 4 . settling time model of the adg5207 part 3 adc driver ad8475 t s_adg5207 t s_AD8251 t s_ad8475 rc + mux adg5207 part 4 rc + adc ad4003 t s_ad4003 part 2 part 1 pgia AD8251 15142-003 c in adg5207 r on r on r on r on r s r s c in c d c d c s c s c s c s AD8251 s1a s8a d a s1b s8b d b 15142-004
cn-0385 circuit note rev. 0 | page 6 of 13 each channel functions similarly to an rc circuit having an associated time constant that dominates settling time. dynamically switching channels complicates signal settling; at the time channels are switched, the difference between the previous output and the current input produces a kickback transient. this kickback is similar to the one that occurs at the input to the ad4003 as it enters the acquisition phase. for a more detailed description, see the analog dialogue article, front-end amplifier and rc filter design for a precision sar analog-to-digital converter . the circuit in figure 4 was simulated using ni multisim?, as shown in figure 5, with the following component values from the respective device data sheets: ? r on = 250 ? c s = 3.5 pf ? c d = 36 pf ? r in ||c in = 1.25 g||2 pf the input resistance of the AD8251 (r in ) is sufficiently large (1.25 g) to be omitted from simulation. figure 5. multisim settling time model of the adg5207 the simulation results are shown in figure 6. the time required for the output of the adg5207 to settle to 0.001% of 10 v is t s_adg5207 = 188 ns. figure 6. settling time waveforms for the adg5207 simulation model settling time of the AD8251 and ad8475 the AD8251 data sheet specifies its settling time for a variety of input voltage step sizes down to a 0.001% error for each gain configuration. given a load of 10 k and gain setting of 1, the AD8251 can settle a 20 v step at its output to 0.001% in approximately 1 s. the gain of 1 setting requires the most settling time; therefore, the settling time analysis uses 1 s. however, the 1 s number may not be accurate when the AD8251 is driving one of the inputs of the ad8475 , which has an input impedance of 2.92 k instead of 10 k. it is also not possible to ascertain settling time of the AD8251 to 18-bit resolution, because of the nonlinear relationship between settling time and precision. therefore, the best settling time estimation is 0.001% error (or 16-bit resolution). the ad8475 has a settling time specification of 50 ns to 0.001% for a 2 v differential output step. the maximum voltage step size expected on the outputs of the ad8475 is twice the reference voltage (v ref ), or approximately 8 v. assuming that the settling time is proportional to the output voltage step, the settling time to 0.001% (16 bits) for an 8 v step is approximately 200 ns (4 50 ns). the settling time of each amplifier is, therefore, ? t s_AD8251 = 1 s ? t s_ad8475 = 200 ns settling time of the rc noise filter and ad4003 figure 7 shows the equivalent circuit of the inputs of the ad4003 . r ext and c ext are the components in the rc wideband noise filter in front of the adc. r in and c in are the input resistance and capacitance of the ad4003 , respectively. c in is mainly the internal capacitive digital-to-analog converter (dac). c pin is primarily the pin capacitance, and is ignored. the values for these components are as follows: ? r ext = 200 ? c ext = 120 pf ? r in = 400 ? c in = 40 pf figure 7. settling time model of the ad4003 and rc noise filter the ad4003 employs an internal capacitive dac and a charge redistribution algorithm to determine its output code. the conversion process contains two phases, acquisition and conversion. during acquisition, the capacitive dac is connected to the input terminals of the ad4003. during conversion, it is disconnected from the input terminals, and internal logic performs the charge-redistribution algorithm. compared to other pulsar adcs, the ad4003 has a much v2 ?10v xsc1 abc d g t 3.5pf v1 +10v cs1 off cs2 off 3.5pf s1 output mux control +? 1 2 1 2 r on 1 250 ? cd1 36pf c1 2pf 56pf 56pf 100 ? 100 ? r on 2 250 ? 15142-005 4 3 2 volts (v) volts (v) 1 050100 time (ns) 150 200 250 300 ?50 0 10 5 0 ?5 ?10 188ns, +10v 0ns, ?10v output (v) mux ctr (v) 15142-006 c pin ref r in c in d1 d2 in+ or in? gnd gnd gnd r ext ext ad4003 15142-007
circuit note cn- 0385 rev. 0 | page 7 of 13 shorter conversion time , and it allows the user t o return to acquisition phase before the end of c onversion. therefore, if the user run s the adc at slower throughput, there is ha ve more time to settle the kick back. the signal must be settled by the end of the acquisition phase for an accurate conversion. t o maximize the time given for the signal to settle, the multiplexer switches channels immediately after the ad4003 begins its conversion phase. in addition to settling from the multiplexed signal from the output of the ad8475 , the rc noise filter and ad4003 inputs also need to se ttle to the voltage kickback that occurs at the beginning of the acquisition phase. for more information, s ee the analog dialogue article, front - end amplifier and rc filter design for a pr ecision sar analog - to - digital converter . the settling time for the circuit in figure 7 was simulated in ni multisim, as shown in figure 8 . v1 represents the maximum voltage step expected at either input of the ad4003 (from a single - ended output of the ad8475 ). cnv and s1 simulate the ad4003 switching from the conversion phase (occurring when v1 change s value) to the acquisition phase (300 ns after start of conversion). cnv keeps s1 open until 300 ns after v1 steps from 0 v to 4 v to represent the transition from the conversion phase to the acquisition phase. adc_in is the voltage that is sampled by the ad4003 on a cnv rising edge. the settling time for this portion of the system is equal to the time between v1 switching to 4 v (at time = 0 , see figure 9 ) to adc_in settling to 0.001% of 4 v. figure 8 . multisim? settling time model of the ad4003 and rc noise filter the simulation results are shown in figure 9 . the time taken for the output to settle to 0.001% of 4 v is t s_ad4003 = 711 ns. fig ure 9 . settling time waveforms for the ad4003 and rc noise filter simulation model total system settling time the total settling time of the entire circuit shown in figure 1 can now be estimated by calculating the rss of the settling times for each component: ? t s_adg5207 = 188 ns ? t s_AD8251 = 1000 ns ? t s_ad8475 = 200 ns ? t s_ad4003 = 711 ns ? ns 1257 ns 11 7 ns 200 s 1 ns 188 t 2 2 2 2 s_total + + + = the expected maximum channel switching sample rate of the system is then ksps 795 ns 1257 1 < sr f offset and gain error results table 4 shows the offset error measured (in l sbs) for each of the channels in each gain configuration for the circuit in figure 1 . table 4 also shows the average offset error of all of the channels for each gain configuration. the offset errors were measured by grounding all of the channel inputs and collecting and averaging 32, 768 samples taken on each of the channels in each gain configuration. table 4 . offset error measurements for all channels and gain configurations (error in lsbs) gain channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel average 0.4 1.34 1.33 1.31 1.36 1.44 1.45 1.46 1.48 1.40 0.8 1.98 1.99 2.02 2.06 2.00 1.98 1.99 1.97 2.00 1.6 3.25 3.19 3.22 3.19 3.17 3.08 3.13 3.14 3.17 3.2 5.57 5.66 5.67 5.55 5.57 5.50 5.54 5.52 5.57 xsc1 a b c d g t not u1 c2 40pf cnv phase 0v 3.3v 300ns 10s v1 0v 4v 5s 10s cnv adc_in r2 400 s1 + ? c1 120pf v1 rc_ext r1 200 15142-008 time (s) adc_in v1 4.0v 4.0v 3.3v 4.0v cnv rc_ext 711ns, 4v 15142-009
cn- 0385 circuit note rev. 0 | page 8 of 1 3 table 5 shows the gain error measured for each of the gain configurations for the circuit in figure 1 . the %fs error was found using the analysis methods described previously , and the actual gain in v/v was calculated by subtracting this error from the ideal gain. table 5 . gain error measurements for all gain configurations gain gain error (%fs) 0.4 0.02 0.8 0.02 1.6 0.03 3.2 0.02 performance results w ithout channel switching figure 10, figure 11, figure 12 , and figure 13 show the fast fourier transform ( fft) plots for a 10 khz , full - scale , sine wave input on a single channel for gain configurations of 0.4, 0.8, 1.6, and 3.2, respectively. table 6 shows the snr and rms noise measured for each of the gain configurations. table 6 . snr, noise, and thd vs. gain for 10 khz input gain snr (db) rms noise (v rms) thd (db) 0.4 93.9 55.2 ?99.2 0.8 92.8 62.6 ?98.5 1.6 90.6 80.7 ?97.0 3.2 88.0 108.9 ?94.6 the input signal was supplied by an audio precision sys - 2700 series signal generator, with the board set in differential input mode. figure 14 shows total harmonic distortion (thd) measurements vs. the frequency of the input signal for each gain configuration. figure 10 . fft for 10 khz, 20 v p - p input for gain = 0.4 on single, static channel figure 11 . fft for 10 khz, 10 v p - p input for gain = 0.8 on single, static channel figure 12 . fft f or 10 khz, 5 v p - p input for gain = 1.6 on single, static channel figure 13 . fft for 10 khz, 2.5 v p - p input for gain = 3.2 on single, static channel ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 amplitude (dbfs) frequency (khz) f s = 1.5msps f in = 10khz snr = 92.52db thd = ?93.96db 15142-010 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 amplitude (dbfs) frequenc y (khz) f s = 1.5msps f in = 10khz snr = 91.48db thd = ?94.35db sinad = 89.67db 15142-0 1 1 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 amplitude (dbfs) frequency (khz) f s = 1.5msps f in = 10khz snr = 90.25db thd = ?94.12db sinad = 88.76db 15142-012 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 frequenc y (khz) f s = 1.5msps f in = 10khz snr = 87.77db thd = ?93.27db sinad = 86.69db 15142-013
circuit note cn- 0385 rev. 0 | page 9 of 13 figure 14 . thd measured for various input frequenc ies on a single, static channel system performance with channel switching several tests were performed to evaluate the performance of the system when scanning multiple channels. experiments using precision dc sources measured the error in output code with respect to sample rate (see the circuit note cn - 0269 for similar tests) and voltage step size between channels. ac performance was also measured for switching between two out of phase, full - scale inputs from a precision ac source (audio precision ap sys - 2712). figure 15 and figure 16 show the test setup for dc and ac performance tests, respectively. the channel switching rate is the rate at which the adg5207 switches from one chann el to another, and is equivalent to the sample rate of the ad4003. figure 15 . settling time evaluation setup using dc calibrators figure 16 . settling time evaluation setup using ac signal generator the dc tests involved varying the voltage step size between the two channels and the channel switching rate. the channel switching rate was varied from 50 khz to 1 mhz in 50 khz increments. the v oltage step size was varied over different ranges for each of the gain configurations. a mean code result was measured for each channel for each voltage step size and channel switching rate by averaging 8,192 samples taken on each channel. a mean code resu lt was also measured for each channel in the static case (no switching between channels). the mean code errors discussed below were found by taking the difference between the mean codes measured for the static case and for the switching channels. figure 17, figure 18, figure 19 , and figure 20 show the mean code error for various voltag e step sizes at several switching rates in each of the four gain configurations. figure 21, figure 22, figure 23 , and figure 24 show the mean code error for full - scale voltage steps at various switching rates in each of the four gain configurations. figure 17 . mean code error vs. voltage step size, gain = 0.4 figure 18 . mean code error vs. voltage step size, gain = 0.8 ?120 ?100 ?80 ?60 ?40 ?20 0 1 10 100 thd (db) input frequenc y (khz) gain = 0.4db gain = 0.8db gain = 1.6db gain = 3.2db 15142-014 e v al-cn0385-fmcz c1? c1+ c2+ c2? gnd + ? dvc dvc + ? ev al-sdp-ch1z 15142-015 e v al-cn0385-fmcz c5? c5+ c7? c7+ gnd e v al-sdp-ch1z + g ap sys-2712 + ? ? g ada4627 buffers 15142-016 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 0 5 10 15 20 mean code error ste p size (v) 100ksps, channel a 100ksps, channel b 500ksps, channel a 500ksps, channel b 800ksps, channel a 800ksps, channel b 15142-017 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 350 0 5 10 15 20 mean code error ste p size (v) 100ksps, channel a 100ksps, channel b 500ksps, channel a 500ksps, channel b 800ksps, channel a 800ksps, channel b 15142-018
cn- 0385 circuit note rev. 0 | page 10 of 13 figure 19 . mean code error vs. voltage step size, gain = 1.6 figure 20 . mean code error vs. voltage step size, gain = 3.2 figure 21 . mean code error vs. channel switching rate for full - scale input step, gain = 0.4 figure 22 . mean code error vs. channel switching rate for full - scale input step, gain = 0.8 fig ure 23 . mean code error vs. channel switching rate for full - scale input step, gain = 1.6 figure 24 . mean code error vs. channel switching rate for full - scale input step, gain = 3.2 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 350 0 5 10 15 20 mean code error ste p size (v) 100ksps, channel a 100ksps, channel b 500ksps, channel a 500ksps, channel b 800ksps, channel a 800ksps, channel b 15142-019 ?100 ?50 0 50 100 150 200 250 300 0 5 10 15 20 mean code error ste p size (v) 100ksps, channel a 100ksps, channel b 500ksps, channel a 500ksps, channel b 800ksps, channel a 800ksps, channel b 15142-020 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 0 200 400 600 800 mean code error channe l switching r a te (khz) 15142-021 +fs ?fs ?400 ?300 ?200 ?100 0 100 200 300 400 500 0 200 400 600 800 mean code error channe l switching r a te (khz) 15142-022 +fs ?fs ?300 ?200 ?100 0 100 200 300 400 500 0 200 400 600 800 mean code error channe l switching r a te (khz) 15142-023 +fs ?fs ?400 ?300 ?200 ?100 0 100 200 300 400 0 200 400 600 800 mean code error channe l switching r a te (khz) +fs ?fs 15142-024
circuit note cn-0385 rev. 0 | page 11 of 13 the mean code error increases as the voltage step size and channel switching rate increase. this increase is caused by the combined slew and settling time limitations of the components in the signal chain. increasing the step size forces the system to settle larger changes in voltage and increasing the channel switching rate decreases the amount of time the system is given to settle these changes. at sufficiently high step sizes and switching rates, the mean code error becomes unpredictably large, as in the gain of 0.4 configuration (see figure 17 and figure 21). this code error is caused by the slew rate limitations of the input buffer amplifiers in the AD8251 in-amp. the performance of the system when using the ac source was evaluated by comparing its thd with respect to the channel switching rate. the ap sys-2712 provided a full-scale sine wave input on one channel and an inverted version of the sine wave on another channel. thd was measured for various sample rates, ranging from 25 ksps to 1.5 msps in 25 ksps increments. figure 25 shows the thd measured for each of the channels in each of the gain configurations. figure 25. thd vs. adg5207 channel switching rate for full-scale 1 khz input the thd performance of the system begins to degrade at roughly 700 ksps (depending on the gain configuration). the whole signal chain snr and thd performance is mainly limited by the pga AD8251 . a smaller rc filter at the front of ad4003 also gives better thd at higher channel switching sampling rate. common variations the ad4003 adc is pin-for-pin compatible with various other 14-bit, 16-bit, and 18-bit, 10-lead precision sar adcs that can be used in the cn-0385 system. the adg1207 , with wider bandwidth, can be an alternative to the adg5207 . the adg5248f , with fault protection and detection function, can be used for single-ended inputs. the ad8475 provides a differential output signal for other differential adcs, such as the ad7690. the ada4805-1 op amp is an alternative for the ad8475 when driving pseudo differential or single-ended adcs, such as the ad4000 . other analog devices, inc., ldos, such as the adp7102 and adp7142 , can replace the adp7118 . circuit evaluation and test this circuit uses the eval-cn0385-fmcz circuit board and the eval-sdp-ch1z sdp-h1 system demonstration platform controller board. the two boards have 160-pin mating connectors, allowing quick setup and evaluation of the performance of the circuit. the circuit board contains the circuit to be evaluated, as described in this circuit note, and the sdp-h1 controller board is used with the cn-0385 evaluation software to capture the data from the circuit board. equipment needed the following equipment is needed: ? pc with a usb port and windows? xp or windows vista? (32-bit), or windows 7 (32-bit) ? eval-cn0385-fmcz circuit evaluation board ? eval-sdp-ch1z sdp-h1 controller board ? cn-0385 evaluation software (download from ftp://ftp.analog.com/pub/cftl/cn0385/ ) ? 5 v to 12 v dc power supply or wall wart (9 v wall wart included with eval-cn0385-fmcz board) ? usb to micro-usb cable ? low distortion, low output impedance signal generator to provide 10 v output ? low noise, high precision dc supply to provide 10 v output getting started download the evaluation software from ftp://ftp.analog.com/ pub/cftl/cn0385/ , and then install the software on the pc. functional block diagram see figure 1 for the circuit block diagram and the eval-cn0385- fmcz-sch.pdf file for the complete circuit schematic. this file is contained in the cn-0385 design support package (available at www.analog.com/cn0385-designsupport ). a functional block diagram of the test setup is shown in figure 26. figure 26. test setup functional block diagram hardware setup figure 27 shows the eval-cn0385-fmcz evaluation hardware. information and details regarding the sdp-h1 board can be found in the sdp-h1 user guide . connect the 160-pin connector on the circuit board to the j4 connector on the sdp-h1 controller board. ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 0 200 400 600 800 thd (db) channe l switching rate (khz) gain = 0.4db gain = 0.8db gain = 1.6db gain = 3.2db 15142-025 eval-cn0385-ch1z p1 p2/ p8 j1/p3 eval-sdp-ch1z usb pc 5v to 12v power ac/dc source(s) 15142-026
cn-0385 circuit note rev. 0 | page 12 of 13 first, connect a 5 v to 12 v dc wall wart to the p3 dc jack or to terminal block j1 and jumper j2 on position v_ext. or, place j2 in position v_fmc to use the 12 v supply from the sdp-h1 board. then connect the sdp-h1 board to the pc via the usb to micro-usb cable. test with the power supply or dc wall wart and usb cable connected, launch the evaluation software. when usb communications are established, the sdp-h1 board can be used to send, receive, and capture data from the eval-cn0385-fmcz board and perform data analysis in the time and frequency domains. information and details regarding test setup and calibration, and how to use the evaluation software for data capture can be found in the cn-0385 software user guide (available at www.analog.com/cn0385-userguide ). figure 27. eval-cn0385-fmcz evaluation hardware 15142-027
circuit note cn-0385 rev. 0 | page 13 of 13 learn more cn-0385 design support package: www.analog.com/cn0385-designsupport ug-502. sdp-h1 user guide. analog devices. ardizzoni, john. a practical guide to high-speed printed-circuit- board layout, analog dialogue 39-09, september 2005. kester, walt. multichannel data acquisition systems in data conversion handbook , chapter 8, section 8.2. elsevier. pachchigar, maithil. complete sensor-to-bits solution simplifies industrial data-acquisition system design, analog dialogue 47-04, april 2013. pachchigar, maithil. demystifying high-performance multiplexed data-acquisition systems, analog dialogue 48-07, july 2014. walsh, alan. front-end amplifier and rc filter design for a precision sar analog-to-digital converter, analog dialogue 46-12, december 2012. an-359 application note. settling time of operational amplifiers . analog devices. an-931 application note. understanding pulsar adc support circuitry . analog devices. an-1024 application note. how to calculate the settling time and sampling rate of a multiplexer . analog devices. an-1264 application note. precision signal conditioning for high resolution industrial applications. analog devices. mt-004 tutorial. the good, the bad and the ugly aspects of adc input noise C is no noise good noise? analog devices. mt-046 tutorial. op amp settling time . analog devices. mt-048 tutorial. op amp noise relationships: 1/f noise, rms noise and equivalent noise bandwidth . analog devices. data sheets and evaluation boards cn-0385 circuit evaluation board (eval-cn0385-fmcz) system demonstration platform (eval-sdp-ch1z) ad4003 data sheet AD8251 data sheet adg5207 data sheet ada4807-2 data sheet ad8475 data sheet adr4540 data sheet adum141e data sheet adp7118 data sheet adp7182 data sheet adp5070 data sheet adum3470 data sheet adp2441 data sheet revision history 10/2016revision 0: initial version (continued from first page) circuits from the lab reference designs are intended only for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the circuits from the lab reference designs in the design of your product, no other license is granted by imp lication or otherwise under any patents or other intellectual property by application or use of the circuits from the lab reference designs. information furnished by analog devices is belie ved to be accurate and reliable. however, circuits from the lab reference designs are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for a ny infringements of patents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuits from the lab reference designs at any time without notice but is under no obligation to do so. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. cn15142-0-10/16(0)

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